The present invention relates to electronics, and more particularly, to semiconductor devices and methods of fabricating the same.
Increases in integration densities of semiconductor devices, such as dynamic random access memory (DRAM) devices, has led to reductions in the area occupied by various semiconductor elements in the semiconductor devices. Capacitances of memory cells, however, should be maintained and/or increased. Methods used to ensure a sufficient cell capacitance within a limited area include use of a high dielectric material for a dielectric layer, reducing the thickness of a dielectric layer, and increasing the effective area of a lower electrode. Of these methods, increasing the effective area of a lower electrode has been employed most often in practical processes.
To increase the effective area of the lower electrode, three-dimensional lower electrodes (such as cylindrical or fin shaped or stack type lower electrodes), hemispherical grains (HSGs) on lower electrodes, and increased heights of lower electrodes have been proposed. In the case of cylindrical or stack type lower electrodes, external surfaces of both of the external and internal surfaces of the lower electrodes may be used, so that the lower electrodes may have relatively large effective areas. However, for cylindrical or stack type lower electrodes having an integrated one cylinder stack (OCS) structure, heights of the lower electrodes should be increased to ensure a capacitance sufficient for operation of a semiconductor device.